DDR PHY Sr. Design Engineer
FMC develops ferroelectric emerging Non-Volatile Memory solutions for stand-alone and embedded applications. Having emerged as a dynamic spin-off from TU Dresden/NaMLab in 2016, we have progressed beyond the startup phase to solidify our position as a significant player in the Memory industry. We are pursuing the once-in-a-lifetime opportunity to establish a brand-new memory product in a market that is craving this innovation.
If you’re ready to contribute your expertise to our dynamic team and play a pivotal role in driving our success, we invite you to apply for the position of DDR PHY Senior Design Engineer (m/f/d) at FMC.
Your future job:
- Responsible for the design and verification of high-speed DDR PHY interface
- Design transmitter, receiver, DLL, ODT and all PHY related circuitry
- Work closely with layout designers to provide guidelines and feedback to achieve robust design
- Run post-layout simulations and verify proper signal integrity
- Verify compliance with JEDEC specifications
Your profile
- Sc. / Ph.D. in electrical engineering
- 8+ years of experience in high speed interface design
- DDR4 PHY design experience for memory or controller devices
- Familiarity with industry-standard design and simulation tools (e.g., Cadence® DFII, Virtuoso, Spice simulator, Verilog-A)
Period: Planned starting date ASAP
We offer:
Benefits includes inspiring work environment, flat hierarchies, opportunity for personal and professional growth (including complimentary training opportunities), multi-cultural team, regular team events, Urban Sports Club membership, free public transportation ticket or fuel voucher, lunch allowance and a competitive salary in a semiconductor environment.
For further questions or to apply please contact:
Lisa Leinemann
Senior HR Manager
Tel.: +49 351 271 88347
career@ferroelectric-memory.com
